Funct. Mater. 2020; 27 (1): 203-209.


Effects of interface roughness on thermal stress in through silicon via structure

Liwen Zhang, Yang Li, Na Li, Jincan Zhang, Zhi Li

School of Electrical Engineering, Henan University of Science and Technology, 471023 Luoyang, Henan, China


Through silicon via (TSV) is the key technology in a three-dimensional packaging structure. The thermal failure problem due to the thermal mismatch under thermal loads in TSVs limits its applicability. To study the thermal reliability, most researchers assume that the interface between silicon and copper is an ideal smooth plane. In fact, the TSV interface has a "scallop" profile sidewall which is formed in "Bosch" via etching process. Based on the analysis of TSV structure models with a "scallop" interface, both radial and shear stresses under thermal loads are simulated and the effects of rough interface on the stress distribution are analyzed. The results show that compared with the stress distribution in the TSV with smooth interface, the stress distribution in the TSV with "scallop" interface is obviously different; there are obvious stress discontinuity extreme points along the rough interface. The stress along the interface changes periodically in accordance to the "scallop" profile from the surface to the inside. The radial stress extreme points almost locate on the tips of the rough interface; the shear stress extreme points almost locate between the curve apex and the curve bottom. With increased interface roughness, the maximal radial and shear stresses also increase.

through silicon via, interface, thermal stress, roughness.
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